A capacitance method to determine the gate-to-drain/Source overlap length of MOSFET's

1 June 1987

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 8 (6) , 269-271
https://doi.org/10.1109/edl.1987.26626

Abstract

A method is described which uses accurate measurement of gate-to-drain/source overlap capacitances to determine the gate-to-drain/ source overlap length for process control as well as device characterization. The method might also be a useful analytical tool in studying lateral dopant diffusion. Using this technique, the variation in overlap length of MOSFET's in a 4-in wafer is mapped. It is found that a significant spread of the overlap exits and is attributable to the implant shadowing by the polysilicon gate.

Keywords

CAPACITANCE MEASUREMENT
IMPLANTS
PARASITIC CAPACITANCE
SHADOW MAPPING
SILICON
FABRICATION
LENGTH MEASUREMENT
PROCESS CONTROL
VERY LARGE SCALE INTEGRATION
CAPACITANCE-VOLTAGE CHARACTERISTICS

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