Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs
- 1 April 2006
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 293-294
- https://doi.org/10.1109/fccm.2006.65
Abstract
The paper presents an architecture and an implementation of an FPGA-based sparse matrix-vector multiplier (SMVM) for use in the iterative solution of large, sparse systems of equations arising from finite element method (FEM) applications. The architecture is based on a pipelined linear array of processing elements (PEs). A hardware-oriented matrix "striping" scheme is developed which reduces the number of required processing elements. The current 8 PE prototype achieves a peak performance of 1.76 GFLOPS and a sustained performance of 1.5 GFLOPS with 8 GB/s of memory bandwidth. The SMVM-pipeline uses 30% of the logic resources and 40% of the memory resources of a Stratix S80 FPGA. By virtue of the local interconnect between the PEs, the SMVM-pipeline obtain scalability features that is only limited by FPGA resources instead of the communication overheadKeywords
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