Performance issues in VC-merge capable switches for IP over ATM networks

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Abstract
VC merging allows many routes to be mapped to the same VC label, providing a scalable mapping method that can support tens of thousands of edge routers. VC merging requires reassembly buffers so that cells belonging to different packets intended for the same destination do not interleave with each other. The impact of VC merging on the additional buffer required for the reassembly buffers and other buffers due to the perturbation in the traffic process is investigated. We propose a realistic output-buffered ATM switch architecture that supports VC merging capability. We analyze the performance of the switch using a decomposition approach, and verify the results using simulation. We investigate the impact of VC merging on loss and delay performance for realistic traffic scenarios. The main result indicates that VC merging incurs a minimal overhead compared to non-VC merging in terms of additional buffering. Moreover, the overhead decreases as utilization increases, or as the traffic becomes more bursty. The finding has important implication since practical ATM switches are dimensioned for high utilization and stressful traffic conditions. We also study the delay performance and find that the additional delay due to VC merging is insignificant for most applications.

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