Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design
- 1 January 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 2 (1) , 18-29
- https://doi.org/10.1109/tcad.1983.1270017
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- A design of CMOS polycell for LSI circuitsIEEE Transactions on Circuits and Systems, 1981
- A dense gate matrix layout method for MOS VLSIIEEE Transactions on Electron Devices, 1980
- Twin-tub CMOS - A technology for VLSI circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1980
- MOTIS-An MOS timing simulatorIEEE Transactions on Circuits and Systems, 1975