Design Technique of Fail-Safe Sequential Circuits Using Flip-Flops For Internal Memory
- 1 November 1974
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-23 (11) , 1149-1154
- https://doi.org/10.1109/t-c.1974.223822
Abstract
A method for the realization of fail-safe sequential circuits is presented where flip-flops are employed for representing the internal states. First, such a design technique where the circuit will be trapped in an erroneous state into which it is transferred by a fault is shown. Further, the condition for assuring that the circuit will be dropped into the particular (predetermined) final state when a fault exists is described. Finally, some extensions of the technique are attempted.Keywords
This publication has 7 references indexed in Scilit:
- On-Set Realization of Fail-Safe Sequential MachinesIEEE Transactions on Computers, 1974
- N-Fail-Safe Sequential MachinesIEEE Transactions on Computers, 1972
- Realization of Fail-Safe Sequential Machines by Using a k-out-of-n CodeIEEE Transactions on Computers, 1971
- Failsafe Logic NetsIEEE Transactions on Computers, 1971
- Systematic Procedures for Realizing Synchronous Sequential Machines Using Flip-Flop Memory: Part IIIEEE Transactions on Computers, 1970
- Systematic Procedures for Realizing Synchronous Sequential Machines Using Flip-Flop Memory: Part IIEEE Transactions on Computers, 1969
- Basic Properties and a Construction Method for Fail-Safe Logical SystemsIEEE Transactions on Electronic Computers, 1967