Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology

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Abstract
System-on-chip (SOC) and system-on-package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS technology densities, a range of two and three dimensional silicon integration technologies are emerging which likely support next generation high-volume electronic applications and may serve high-performance computing applications. This paper discusses a few emerging technologies which offer opportunities for circuit integration on-chip as well as on-package using fine pitch interconnection, silicon wafer processing and silicon carrier packaging technology. Advanced silicon carrier package technology with fine pitch (50μm) interconnection is described. This silicon carrier package contains silicon through-vias and offers >16× increase over standard chip I/O, a 20× to 100× increase in wiring density over traditional organic and ceramic packaging, and allows for integrated high performance passives. Silicon carrier technology supports lithographic scaling and provides a basis for known good die (KGD) wafer testing. It may be considered for use in a number of applications including optoelectronic (OE) transceivers and mini-multi-chip modules (MMCM) which integrate heterogeneous dies forming a single "virtual chip".

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