Reducing compilation time of Zhong's FPGA-based SAT solver

20 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 308-309
https://doi.org/10.1109/fpga.1999.803709

Abstract

We present schemes to reduce the compilation time of configurable hardware that solves Boolean satisfiability. The SAT solver presented by Zhong et al. (1998) has a large compilation time overhead mainly due to placement and routing of many FPGAs. We attack the problem on three fronts. First, we partition the SAT solver into instance-specific and instance non-specific components. Secondly, we transform SAT instances into canonical forms; and finally we present a board-level multiple-chip architecture to solve large SAT instances. All these efforts amount to a reduction in placement and routing time to configure the configurable hardware. We are able to reduce the compilation time to mere routing time of the implication circuits for each instance of the SAT problem, given the best scenario.

Keywords

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