Optimized synchronous rectification stage for low output voltage (3.3 V) DC/DC conversion
- 1 June 1994
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 2, 902-908 vol.2
- https://doi.org/10.1109/pesc.1994.373786
Abstract
A new strategy to obtain low output voltage (3.3 V) is presented in this paper. The output stage is optimized to minimize losses in the self-driven synchronous rectifiers, by means of a fixed frequency, fixed duty cycle (0.5) driving waveform. The output voltage is controlled by a high switching frequency preregulator. This preregulator can be removed if input voltage variation is low. Very high efficiency (93%) has been obtained in an actual prototype (3.3 V and 20 A) of the optimized SR stage.Keywords
This publication has 7 references indexed in Scilit:
- Self driven synchronous rectification in resonant topologies: forward ZVS-MRC, forward ZCS-QRC and LCC-PRCPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A simple and efficient synchronous rectifier for forward DC-DC convertersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A MOSFET resonant synchronous rectifier for high-frequency DC/DC convertersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Resonant reset forward topologies for low output voltage on board convertersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1994
- RCD clamp PWM forward converter with self driven synchronous rectificationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- Active clamp PWM forward converter with self driven synchronous rectificationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- Study of the applicability of self-driven synchronous rectification to resonant topologiesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992