Stress Effect on the Reliability of pMOS TFTs for 16 Mb SRAM: DC Stress at Room and Elevated Temperatures

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Abstract
We present a systematic experimental study of the electrical stress effects in p-channel metal-oxide-semiconductor thin film transistors (pMOS TFTs) used as active loads in high density static random access memory (SRAM) circuits. Specifically, the effects of dc stresses occurring during standby were investigated in devices both with and without offset and at room and elevated substrate temperatures. The stresses associated with the OFF regime biases give rise to a drastic reduction of leakage current and at the same time, a significant increase in the ON current. These effects are particularly pronounced in devices without offset and for stress biases applied at room temperature or below. Although at elevated substrate temperature the leakage current itself is enhanced by a few orders of magnitude, the stress-induced parameter shifts are shown to be smaller than those at lower temperatures. Additionally, the stress induced reliability aspects of pMOS TFTs used for 4 Mb and 16 Mb SRAM are compared and discussed.

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