An ECL compatible 4K CMOS RAM

1 January 1982

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXV, 248-249
https://doi.org/10.1109/isscc.1982.1156338

Abstract

This paper will discuss a 4K×1 ECL compatible static RAM using a HMOSII/CMOS process and speed-optimized CMOS circuits. Input and output levels have been found to meet specifications of the ECL 10K logic family. Address access time is 20ns and current drain is 150mA under nominal conditions.

Keywords

VOLTAGE
CMOS TECHNOLOGY
SWITCHES
CMOS LOGIC CIRCUITS
READ-WRITE MEMORY
INVERTERS
DELAY
DRIVER CIRCUITS
PULSE AMPLIFIERS
MOS DEVICES

This publication has 1 reference indexed in Scilit:

HMOS-CMOS technology
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1981