A high performance MOSFET design with highly controllable gate length and low RC delay multilevel interconnects technology for high speed logic devices

19 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 705-708
https://doi.org/10.1109/iedm.1995.499316

Abstract

A high performance 0.3 /spl mu/m CMOS technology has been developed for high speed logic LSIs. A new gate formation technology achieved 0.3 /spl mu/m gate length MOSFETs by i-line based lithography and new ARC process. An optimized PLDD nMOSFET and buried channel pMOSFET achieved high current drivability without spoiling their reliability in 3.3 V operation. Moreover, ion implantation restricted only for channel/isolation region and SiOF low interlayer dielectric process reduced junction capacitance and wiring capacitance, respectively. Furthermore, CMP planarization process and selective CVD-W filling for contacts/vias achieved borderless design with the improvement of device density. The 0.3 /spl mu/m CMOS technology has performed 1.2 times improvement from conventional 0.35 /spl mu/m CMOS technology in a typical critical path of advanced MPUs.

Keywords

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