Multilevel logic synthesis
- 1 January 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Proceedings of the IEEE
- Vol. 78 (2) , 264-300
- https://doi.org/10.1109/5.52213
Abstract
No abstract availableKeywords
This publication has 48 references indexed in Scilit:
- Design automation tools for efficient implementation of logic functions by decompositionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- The transduction method-design of logic networks based on permissible functionsIEEE Transactions on Computers, 1989
- Multi-level logic minimization using implicit don't caresIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- SOCRATES: a highly efficient automatic test pattern generation systemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Synthesis and Optimization of Multilevel Logic under Timing ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- Comments on a method of KarpovskyInformation and Control, 1978
- Optimal Code Generation for Expression TreesJournal of the ACM, 1976
- An Approach to Multilevel Boolean MinimizationJournal of the ACM, 1964
- Minimization of Boolean Functions*Bell System Technical Journal, 1956