Error analysis and digital correction algorithms for pipelined A/D converters
- 4 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1709-1712
- https://doi.org/10.1109/iscas.1990.111950
Abstract
No abstract availableKeywords
This publication has 2 references indexed in Scilit:
- A pipelined 5-Msample/s 9-bit analog-to-digital converterIEEE Journal of Solid-State Circuits, 1987
- High-accuracy pipeline A/D convertor configurationElectronics Letters, 1985