Performance-augmented CMOS using back-end uniaxial strain

25 June 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 41-42
https://doi.org/10.1109/drc.2002.1029496

Abstract

In this paper we report the first detailed electrical characterization of uniaxially-strained fully-depleted silicon-on-insulator (FD-SOI) n and p-channel MOSFETs. Using the back-end approach, an in-plane, tensile strain was applied to the FD SOI MOSFETs after device manufacture. Dies were thinned to membrane dimensions and then affixed to curved substrates. The die transfer process minimizes edge effects and spurious membrane behavior.

Keywords

UNIAXIAL STRAIN
CAPACITIVE SENSORS
MOSFETS
SILICON
TENSILE STRAIN
ELECTRON MOBILITY
BIOMEMBRANES
TESTING
SCATTERING
ROUGH SURFACES

This publication has 2 references indexed in Scilit:

Uniaxial, tensile-strained Si devices
Journal of Electronic Materials, 2001
Fabrication and analysis of deep submicron strained-Si n-MOSFET's
IEEE Transactions on Electron Devices, 2000