Statistical MOS VLSI circuit optimization with non-nested experimental design
- 6 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1799-1802
- https://doi.org/10.1109/iscas.1988.15285
Abstract
The authors present an efficient method that minimizes the circuit performance sensitivities to the MOSFET parameter fluctuations. A worst-case and squared-error loss function is used to evaluate the noise sensitivity of a design. The statistical circuit performance is modeled as a function of both the transistor channel widths and a noise parameter, and circuit simulation points are selected by an experimental design strategy that assumes no experimental errors. The fitted performance model is then used to predict and optimize the worst-case performance and the squared-error loss function. Compared with the method of G. Taguchi and Y. Wu (1985) in two circuit examples, the proposed method requires about 60% fewer circuit simulations and predicts the loss functions with comparable or better accuracy.> Author(s) Yu, T.K. Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA Kang, S.M.Keywords
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