Use of performance sensitivities in routing analog circuits

Abstract
The use of performance sensitivities in routing of analog circuits is advocated. Performance constraints are modeled in terms of the sensitivities of performance functions with respect to the routing parasitics for both single-ended and differential circuits. Expressions for the worst-case performance sensitivities due to process variations are derived and shown to play an important role in differential circuits. A well-defined procedure for selecting a set of critical parasitics during layout design is presented.

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