A Fast VLSI Multiplier for GF(2m)
- 1 January 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal on Selected Areas in Communications
- Vol. 4 (1) , 62-66
- https://doi.org/10.1109/jsac.1986.1146305
Abstract
Multiplication in the finite field GF(2^{m} ) has particular computational advantages in data encryption systems. This paper presents a new algorithm for performing fast multiplication in GF(2^{m} ), which is O(m) in computation time and implementation area. The bit-slice architecture of a serial-in-serial-out modulo multiplier is described and the circuit details given. The design is highly regular, modular, and well-suited for VLSI implementation. The resulting multiplier will have application in algorithms based on arithmetic in large finite fields of characteristic 2, and which require high throughput.Keywords
This publication has 4 references indexed in Scilit:
- VLSI Architectures for Computing Multiplications and Inverses in GF(2m)IEEE Transactions on Computers, 1985
- Systolic Multipliers for Finite Fields GF(2m)IEEE Transactions on Computers, 1984
- A Cellular-Array Multiplier for GF(2m)IEEE Transactions on Computers, 1971
- Computation with finite fieldsInformation and Control, 1963