A 1V 24GHz 17.5mW PLL in 0.18μm CMOS

• 30 August 2005
• conference paper
• Published by Institute of Electrical and Electronics Engineers (IEEE)
• https://doi.org/10.1109/isscc.2005.1493917

Abstract

Keywords

• CMOS
• CMOS INTEGRATED CIRCUITS
• PHASE NOISE
• PHASE LOCKED LOOPS