An experimental 1Mb DRAM with on-chip voltage limiter

1 January 1984

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXVII, 282-283
https://doi.org/10.1109/isscc.1984.1156686

Abstract

This paper will report on an experimental 21μm ² cell, single 5V 1Mb NMOS DRAM. Typical clata are: access time 90ns, power dissipation 300mW at 260ns cycle time. Chip area is 46mm ²

Keywords

RANDOM ACCESS MEMORY
VOLTAGE
CIRCUITS
POWER DISSIPATION
SIGNAL TO NOISE RATIO
CAPACITORS
CAPACITANCE
DECODING
SWITCHES
READ-WRITE MEMORY

This publication has 1 reference indexed in Scilit:

Submicron VLSI memory circuits
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1983