LDD MOSFETs using disposable sidewall spacer technology
- 1 April 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 9 (4) , 189-192
- https://doi.org/10.1109/55.685
Abstract
A technology for fabricating lightly doped drain (LDD) MOSFET devices based on disposable sidewall spacers is presented. Using a thin polysilicon buffer layer between the low-temperature oxide (LTO) sidewall spacers and the oxidized polysilicon gate, a single masking step can be used to form the n/sup -/ and n/sup +/ or p/sup -/ and p/sup +/ source/drain implants for the NMOS and PMOS devices, respectively. In addition, the LTO sidewall spacers may be removed by a wet HF strip, thus minimizing additional damage to the gate oxide that may be caused by reactive ion etch removal. The disposable sidewall spacer technology is easily adaptable to a CMOS process as demonstrated by the fabrication of a 4 K*4 SRAM circuit using a conventional 1.5- mu CMOS technology.<>Keywords
This publication has 3 references indexed in Scilit:
- Optimum design of n+-n-double-diffused drain MOSFET to reduce hot-carrier emissionIEEE Transactions on Electron Devices, 1985
- Fabrication of high-performance LDDFET's with Oxide sidewall-spacer technologyIEEE Transactions on Electron Devices, 1982
- Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistorIEEE Transactions on Electron Devices, 1980