Synthesis of Error-Tolerant Counters Using Minimum Distance Three State Assignments

Abstract
It is shown that by using minimum distance three state assignments and considering error states when deriving the input equations, counters tolerant of a single error can be synthesized. Although one flip-flop in the counter might be in error, the other flip-flops will continue to sequence correctly. Thus acceptable sequencing continues with a malfunctioning unit present in the circuit. Because of the error correcting properties of the state assignment, the correct state of the counter can be recovered. A one-bit error introduced by noise or an intermittent malfunction will be automatically corrected. Failure occurs if more than one flip-flop is in error. Redundancy is incorporated as an inherent result of the initial design procedure rather than being included after a nonredundant working design is obtained. Instead of using any of the known methods of simplification of Boolean functions, the synthesis procedure involves the selection of a minimum number of terms which satisfy a concise set of distance and intersection properties. The selection procedure is intrinsically suitable for machine computation. Although specific logic units are discussed, it is believed that the concepts are general in nature and can be applied to any type of logic hardware.

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