A nonoverlapping gate charge-coupling technology for serial memory and signal processing applications
- 1 February 1976
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 11 (1) , 203-207
- https://doi.org/10.1109/jssc.1976.1050698
Abstract
Of the many technologies available to implement efficient and stable charge-coupled devices (CCD's), most employ a multilevel metal, overlapping gate approach. As a consequence, the CCD process becomes generally more complex and the resulting overlap capacitance can be embarrassing for serial memory applications. This paper describes a single level aluminium gate process, the notable features of which are simplicity, extremely high yield, low interphase capacitance, and very high packing density. Interelectrode spacings in the range 2000 /spl Aring/-5000 /spl Aring/ are achieved. The performance capability is described in the context of an analog delay line.Keywords
This publication has 2 references indexed in Scilit:
- Surface potential equilibration method of setting charge in charge-coupled devicesIEEE Transactions on Electron Devices, 1975
- Direct comparison of ion−damage gettering and phosphorus−diffusion gettering of Au in SiJournal of Applied Physics, 1975