Area—Time Optimal VLSI Circuits for Convolution
- 1 July 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-32 (7) , 684-688
- https://doi.org/10.1109/tc.1983.1676300
Abstract
A family of VLSI circuits is presented to perform open convolution, i.e., polynomial multiplication. The circuits are all based on a recursive construction and are therefore particularly well adapted to automated design. All the circuits presented are optimal with respect to the area–time2 tradeoff, and, depending on the degree of paralleism or pipeline, they range from a compact but slow convolver to a large but very fast convolver.Keywords
This publication has 4 references indexed in Scilit:
- The Area-Time Complexity of Binary MultiplicationJournal of the ACM, 1981
- Area-time optimal VLSI networks for multiplying matricesInformation Processing Letters, 1980
- A combinatorial limit to the computing power of V.L.S.I. circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1980
- Area-time complexity for VLSIPublished by Association for Computing Machinery (ACM) ,1979