VLSI (Very Large Scale Integrated) Self-Testing Using Exhaustive Bit Patterns

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Abstract
The use of Linear Feedback Shift Register functions in generating exhaustive test case coverage for Very Large Scale Integrated circuits with SCAN/SET capability is presented. Both deterministic and probabilistic approaches to test pattern generation are discussed. A technique for signature generation is presented with analysis of its effectiveness. Also, a technique is described for consolidating the test patttern generation and signature capture functions into a single test/detect capability that requires less built-in hardware for implementation.

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