An improved circuit model for CMOS latchup

1 July 1985

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 6 (7) , 320-322
https://doi.org/10.1109/EDL.1985.26141

Abstract

The traditional n-p-n---p-n-p transistor model for CMOS latchup does not adequately describe the latchup path of modern epitaxial devices, a fact which accounts for its inability to produce satisfactory results for devices having a high holding voltage. In this letter a more physically based equivalent circuit representation is discussed. The model better depicts bulk ohmic voltage drops and is more descriptive of the latchup phenomena in epitaxial CMOS devices.

Keywords

SEMICONDUCTOR DEVICE MODELING
VOLTAGE
SEMICONDUCTOR PROCESS MODELING
P-N JUNCTIONS
PREDICTIVE MODELS
EPITAXIAL LAYERS
RESISTORS
EQUIVALENT CIRCUITS
FEEDBACK
BIPOLAR TRANSISTORS

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