Ultra High Speed Integrated Circuits with Selectively Doped Heterostructure Transistors

1 October 1984

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 129-132
https://doi.org/10.1109/gaas.1984.10401299

Abstract

We report on the performance of ring oscillators and frequency dividers made with SDHTs (Selectively Doped Heterostructure Transistors). Ring oscillators with submicron driver transistor gates have been fabricated using direct e-beam writing. A minimum propagation delay of 11.0 ps was obtained with 0.4 μm gates at 77 K. The speed-power product was 15.0 fJ/gate at 1.1 V bias. A dual-clocked M/S (master/slave) flip-flop frequency divider using 1 Mm dual-gate SDHTs was also fabricated and tested. This is the first implementation of a DCFL circuit with NAND-type logic gates. A maximum dividing frequency of 5.5 (10.1) GHz was achieved at 300 (77) K. Both the 11.0 ps/gate ring oscillator delay and the 10.1 GHz dividing frequency represent the fastest speed reported for such semiconductor circuits.

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