Storage assignment to decrease code size
- 1 May 1996
- journal article
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Programming Languages and Systems
- Vol. 18 (3) , 235-253
- https://doi.org/10.1145/229542.229543
Abstract
DSP architectures typically provide indirect addressing modes with autoincrement and decrement. In addition, indexing mode is generally not available, and there are usually few, if any, general-purpose registers. Hence, it is necessary to use address registers and perform address arithmetic to access automatic variables. Subsuming the address arithmetic into autoincrement and decrement modes improves the size of the generated code. In this article we present a formulation of the problem of optimal storage assignment such that explicit instructions for address arithmetic are minimized. We prove that for the case of a single address register the decision problem is NP-complete, even for a single basic block. We then generalize the problem to multiple address registers. For both cases heuristic algorithms are given, and experimental results are presented.Keywords
This publication has 6 references indexed in Scilit:
- Challenges in Code Generation for Embedded ProcessorsPublished by Springer Nature ,2002
- Code Generation and Optimization Techniques for Embedded Digital Signal ProcessorsPublished by Springer Nature ,1996
- SUIFACM SIGPLAN Notices, 1994
- Optimizing stack frame accesses for processors with restricted addressing modesSoftware: Practice and Experience, 1992
- Trace Scheduling: A Technique for Global Microcode CompactionIEEE Transactions on Computers, 1981
- Register allocation via coloringComputer Languages, 1981