A simulation study of two-level caches

• 6 January 2003
• conference paper
• Published by Institute of Electrical and Electronics Engineers (IEEE)
• https://doi.org/10.1109/isca.1988.5213

Abstract

Keywords

• SIMULATION
• MODEL
• MEMORY
• INSTRUCTION
• SECOND LEVEL
• LEVEL CACHE
• K SECOND
• INCREASES PERFORMANCE