Radix-2 FFT butterfly processor using distributed arithmetic
- 20 January 1983
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 19 (2) , 43-44
- https://doi.org/10.1049/el:19830032
Abstract
A parallel-data VLSI architecture for computation of the fast Fourier transform (FFT) is described. The processor is based on a computationally efficient vector rotate algorithm. Use of a 2-dimensional pipeline configuration allows a radix-2 butterfly operation to be performed once every system clock cycle (250 ns) to generate real or imaginary transform components. The architecture is considered to be a computationally efficient VLSI approach for high-bandwidth computation of the FFT. The design and performance of an 8-bit FFT butterfly processor are described.Keywords
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