Stray-free switched-capacitor unit-delay circuit
- 29 March 1984
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 20 (7) , 308-310
- https://doi.org/10.1049/el:19840211
Abstract
A two-phase stray-insensitive switched-capacitor unit-delay circuit utilising only one operational amplifier is presented. The implementation of sampled analogue filters based on digital-filter architectures using this circuit as a building block is demonstrated. A final application of the unit delay, a switched-capacitor interpolator which effectively doubles the sampling frequency of the output of an analogue discrete-time system, is shown.Keywords
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