PASIC: a smart sensor for computer vision

4 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. ii, 286-291
https://doi.org/10.1109/icpr.1990.119371

Abstract

The processor, A/D converter, sensor integrated circuit (PASIC) prototype chip, which contains 256*256 photosensors, a linear array of 256 A/D converters, two 256 8-b shift registers a 256-bit-serial arithmetic logic unit, and a 256*128-b-dynamic RAM, is presented. It is claimed to be a viable architecture for low-level vision processing. The processors operate in single-instruction multiple-data (SIMD) mode at 20 MHz. When executing an edge-detection algorithm, it is shown that the 256 processors are capable of an output rate of 3 Mpixel/s.

Keywords

This publication has 5 references indexed in Scilit:

Inspection of printed circuit boards by connectivity preserving shrinking
IEEE Transactions on Pattern Analysis and Machine Intelligence, 1988
Architecture and applications of the Connection Machine
Computer, 1988
Design of a Massively Parallel Processor
IEEE Transactions on Computers, 1980
DAP---a distributed array processor
Published by Association for Computing Machinery (ACM) ,1973
Thinning algorithms on rectangular, hexagonal, and triangular arrays
Communications of the ACM, 1972