A Study on a Metal-Ferroelectric-Oxide-Semiconductor Structure with Thin Silicon Oxide Film Using SrBi2Ta2O9 Ferroelectric Films Prepared by Pulsed Laser Deposition
- 1 September 1999
- journal article
- Published by IOP Publishing in Japanese Journal of Applied Physics
- Vol. 38 (9S) , 5432
- https://doi.org/10.1143/jjap.38.5432
Abstract
A preferentially (105)-oriented SrBi2Ta2O9 (SBT) thin film on SiO2/n-Si(100) or on Pt is prepared by pulsed laser deposition (PLD) at a low temperature of about 500°C. Polarization-electric field (P–E) hysteresis is observed on the Pt/SBT/Pt diode, where 2P r is 5 µC/cm2 and E c is 34 kV/cm, respectively. Counterclockwise hysteresis appears in the C–V curve of the Al/SBT/SiO2/Si structure only when a (105) peak is observed under various growth conditions by PLD. This means that (105)-oriented perovskite SBT exhibits counterclockwise hysteresis and noncrystalline SBT does not exhibit hysteresis. The memory window has been increased from 2.7 V to 4.3 V by changing the thickness ratio of SBT/SiO2 from 400 nm/27 nm to 400 nm/8 nm. This shows that an efficient electric field in SBT is increased in the case of 8 nm SiO2 film; then E c and the resulting memory window are also increased. Positive shifts in the C–V curves are observed when SiO2 thickness decreases down to about 10 nm. One of the mechanisms of the shift is considered to be that a negative charge is generated by electron tunneling through the SiO2 from the conduction band of n-Si and is fixed at the SBT/SiO2 interface or in the SBT bulk site. Also, the memory window starts to decrease when the gate bias applied to the MFOS diode is sufficiently increased. This indicates that the charge injection mode becomes dominant then reduces dielectric counterclockwise hysteresis. The retention time has been improved up to about 3×103 sec with an optimized hold bias voltage in an MFOS diode with SiO2 thickness of 27 nm.Keywords
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