CMOS device isolation using the selective-etch-and-refill-with-EPI (SEREPI) process

1 December 1985

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 6 (12) , 617-619
https://doi.org/10.1109/edl.1985.26251

Abstract

A technique has been developed for forming wells in a silicon substrate for CMOS IC's with an oxide layer providing lateral isolation between adjacent devices. The silicon in the wells is etched; oxide is formed on the sidewalls of the wells; and the wells are refilled with selectively deposited epitaxial silicon. Ring oscillators and submicrometer n- and p-channel MOS transistors have been fabricated using this isolation technique, and special latch-up test structures have been investigated.

Keywords

CMOS PROCESS
SILICON
ETCHING
SUBSTRATES
ANISOTROPIC MAGNETORESISTANCE
RING OSCILLATORS
GEOMETRY
FABRICATION
MOSFETS
CIRCUIT TESTING

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