An 18-bit floating-point signal processor VLSI with an on-chip 512W dual-port RAM

Publisher Website

23 March 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/icassp.1985.1168489

Abstract

No abstract available

Keywords

This publication has 2 references indexed in Scilit:

Adaptive bit allocation scheme in predictive coding of speech
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
Hierarchical top-down layout design method for VLSI chip
Published by Association for Computing Machinery (ACM) ,1982