Soft Error Rate Analysis Model (SERAM) for Dynamic NMOS RAMs

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Abstract
Soft Error Rate Analysis Model (SERAM) for dynamic NMOS RAMs is developed. SERAM simulates the three-dimensional diffusion and collection processes of alpha-particle induced carriers for various incidences. To verify SERAM, the frequency of collected charge in one memory cell and soft error rates of 64 K-bit samples were measured. The simulations were in good agreement with the experiments. Memory cell scaling analysis by SERAM shows that if the cell area scales as (1/K)2, the ratio Q c /Q α decreases as (1/K)β, where K>1, β∼0.4 for unsealed voltages, and Q c and Q α are the critical charge and the noise charge, respectively.

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