Analysis of a packet switch with input and output buffers and speed constraints
- 1 January 1991
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 694-700 vol.2
- https://doi.org/10.1109/infcom.1991.147573
Abstract
A nonblocking N*N switch for high speed packet switching networks is considered. In practice such a switch may operate L times faster than the input/output trunk. When 1Keywords
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