A 160 ns 54 bit CMOS division implementation using self-timing and symmetrically overlapped SRT stages

This publication has 8 references indexed in Scilit:

• An NMOS 64b floating-point chip set
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
• Algorithm for high speed shared radix 8 division and radix 8 square root
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• A Zero-overhead Self-timed 160ns 54b CMOS Divider
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1991
• SPIM: a pipelined 64*64-bit iterative multiplier
  IEEE Journal of Solid-State Circuits, 1989
• Automatic synthesis of asynchronous circuits from high-level specifications
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
• Radix 16 SRT dividers with overlapped quotient selection stages: A 225 nanosecond double precision divider for the S-1 Mark IIB
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1985
• A high performance floating point coprocessor
  IEEE Journal of Solid-State Circuits, 1984
• Higher-Radix Division Using Estimates of the Divisor and Partial Remainders
  IEEE Transactions on Computers, 1968