The Wisconsin multicube: a new large-scale cache-coherent multiprocessor

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Abstract
The Wisconsin Multicube , is a large-scale, shared-memory multiprocessor architecture that employs a snooping cache protocol over a grid of buses. Each processor has a conventional (SRAM) cache optimized to minimize memory latency and a large (DRAM) snooping cache optimized to reduce bus traffic and to maintain consistency. The large snooping cache should guarantee that nearly all the traffic on the buses will be generated by I/O and accesses to shared data. The programmer's view of the system is like a multi -- a set of processors having access to a common shared memory with no notion of geographical locality. Thus writing software, including the operating system, should be a straightforward extension of those techniques being developed for multis. The interconnection topology allows for a cache-coherent protocol for which most bus requests can be satisfied with no more than twice the number of bus operations required of a single-bus multi. The total symmetry guarantees that there are no topology-induced bottlenecks. The total bus bandwidth grows in proportion to the product of the number of processors and the average path length. The proposed architecture is an example of a new class of interconnection topologies -- the Multicube -- which consists of N =n k processors, where each processor is connected to k buses and each bus is connected to n processors. The hypercube is a special case where n =2. The Wisconsin Multicube is a two-dimensional Multicube ( k =2), where n scales to about 32, resulting in a proposed system of over 1,000 processors.

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