MeV-energy As+ implantation into Si: Extended-defect reduction and planar n-p-n transistor fabrication
- 1 October 1983
- journal article
- letter
- Published by AIP Publishing in Journal of Applied Physics
- Vol. 54 (10) , 6041-6043
- https://doi.org/10.1063/1.331749
Abstract
With 2.5 MeV‐As+ implantation into Si, etch‐pit density (after annealing) could be lowered below 104 cm−2, whether D was smaller than 5×10−4 or larger than 2×10−2. Here D stands for damage degree in the as‐implanted sample [0(single‐crystalline)≤D≤1 (amorphous)]. At given doses, D could be controlled to be at its optimal value by wafer temperature (over a range from 25–300 °C). By utilizing such MeV‐energy implantation to form buried collector layers, planar n‐p‐n transistors could be successfully fabricated even without epitaxial growth.This publication has 4 references indexed in Scilit:
- In Situ Self Ion Beam Annealing of Damage in Si during High Energy (0.53 MeV–2.56 MeV) As+ Ion ImplantationJapanese Journal of Applied Physics, 1981
- High Energy As+ Ion Implantation into Si–Arsenic Profiles and Electrical Activation Characteristics–Japanese Journal of Applied Physics, 1981
- New advances in semiconductor implantationJournal of Vacuum Science and Technology, 1978
- Experimental Evaluation of High Energy Ion Implantation Gradients for Possible Fabrication of a Transistor Pedestal CollectorIBM Journal of Research and Development, 1971