SOI technology using buried layers of oxidized porous Si
- 1 November 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Circuits and Devices Magazine
- Vol. 3 (6) , 11-15
- https://doi.org/10.1109/MCD.1987.6323174
Abstract
A process to form large defect-free silicon-on-insulator structures on 4-in wafers, without warpage, using a layer of oxidized porous silicon in an n/n+/n structure is presented. CMOS devices have been fabricated in insulated single-crystal silicon islands. Mobilities comparable to bulk silicon have been measured and low-leakage junctions were realized. The advantages and limitations of the process are discussed.Keywords
This publication has 0 references indexed in Scilit: