500 Mbyte/sec data-rate 512 Kbits*9 DRAM using a novel I/O interface

2 January 2003

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/vlsic.1992.229280

Abstract

A novel 512-kb*9 DRAM with a 500-Mbyte/s data transfer rate has been designed. This high data-rate has been achieved by coupling a very high internal column bandwidth DRAM core with a very high internal column bandwidth, and coupling this core with a block oriented, small-swing, synchronous interface that uses skew canceling clocks. The DRAM has a 1-kbyte*2 line sense amplifier cache. This DRAM is assembled in a 32-pin vertical surface mount type plastic package.

Keywords

RANDOM ACCESS MEMORY
CLOCKS
SIGNAL GENERATORS
BANDWIDTH
LOGIC
MICROELECTRONICS
DIGITAL SYSTEMS
GRAPHICS
CONTENT ADDRESSABLE STORAGE
NOISE REDUCTION

This publication has 1 reference indexed in Scilit:

Decoded-source sense amplifier for high-density DRAMs
IEEE Journal of Solid-State Circuits, 1990