Multi-level logic gate implementation in GaAs ICs using schottky diode-FET logic

1 January 1980

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXIII, 122-123
https://doi.org/10.1109/isscc.1980.1156064

Abstract

An extension of the Schottky diode-FET logic circuit approach for ultra high-speed, low-power planar GaAs digital ICs to configurations allowing up to three levels of logic to be performed in one gate, will be reported.

Keywords

This publication has 5 references indexed in Scilit:

MSI High-Speed Low-Power GaAs Integrated Circuits Using Schottky Diode FET Logic
IEEE Transactions on Microwave Theory and Techniques, 1980
The prospects for ultrahigh-speed VLSI GaAs digital logic
IEEE Journal of Solid-State Circuits, 1979
Planar GaAs IC technology: Applications for digital LSI
IEEE Journal of Solid-State Circuits, 1978
Low power GaAs digital ICs using Schottky diode-FET logic
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1978
GaAs MESFET logic with 4-GHz clock rate
IEEE Journal of Solid-State Circuits, 1977