A static random-access memory with normally-off-type Schottky barrier FET's
- 1 October 1973
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 8 (5) , 326-331
- https://doi.org/10.1109/JSSC.1973.1050412
Abstract
A large-scale integrated memory with lower power consumption and high operating speed has been developed and evaluated. A fully decoded 256-b static random-access memory chip was fabricated by using the Enhancement-type Schottky Barrier gate FET's, having a threshold voltage of 0.1 V, obtained by ion-implantation. The memory chip was successfully operated with an access time of less than 150 ns, and with active power consumption of 15 mW/chip. A single power supply of -1.3 V and current mode logic input levels are additional features of the memory chip.Keywords
This publication has 2 references indexed in Scilit:
- Hafnium-Silicon Schottky Barriers: Large Barrier Height on p-Type Silicon and Ohmic Behavior on n-Type SiliconApplied Physics Letters, 1971
- A diode-coupled bipolar transistor memory cellPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1970