Fabrication Technology and Device Performance of Sub-50-nm-Gate InP-Based High Electron Mobility Transistors

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Abstract
We fabricated sub-50-nm-gate InAlAs/InGaAs high electron mobility transistors (HEMTs) lattice-matched to InP substrates. The two-step-recessed gate technology and low-temperature process, with all steps taking place below 300°C, allowed us to fabricate sub-50-nm-gate HEMTs that had high levels of performance. We succeeded in fabricating ultrashort 25-nm-long T-shaped gates. DC measurements showed that the 25-nm-gate HEMT had good pinchoff behavior, and that its maximum transconductance gm was about 770 mS/mm. A cutoff frequency fT of 396 GHz was obtained for the 25-nm-gate HEMT. This fT is the highest value yet reported for a transistor of any type, and the gate length of 25 nm is the shortest value ever reported for any compound semiconductor transistor that exhibits true device operation.

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