A Two's Complement Parallel Array Multiplication Algorithm
- 1 December 1973
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-22 (12) , 1045-1047
- https://doi.org/10.1109/t-c.1973.223648
Abstract
An algorithm for high-speed, two's complement, m-bit by n-bit parallel array multiplication is described. The two's complement multiplication is converted to an equivalent parallel array addition problem in which each partial product bit is the AND of a multiplier bit and a multiplicand bit, and the signs of all the partial product bits are positive.Keywords
This publication has 1 reference indexed in Scilit:
- A 40-ns 17-Bit by 17-Bit Array MultiplierIEEE Transactions on Computers, 1971