Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology

1 January 2004

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 50-51
https://doi.org/10.1109/vlsit.2004.1345387

Abstract

We describe the device physics of uniaxial strained silicon transistors. Uniaxial strain is more effective, less costly and easier to implement. The highest PMOS drive current to date is reported: 0.72mA/ /spl mu/m. Pattern sensitivity and mobility/Rext partitioning are discussed. Finally we measure inverter delays as low as 4.6pS, and show 50Mb SRAMs operational at 0.65V.

Keywords

CMOS TECHNOLOGY
DELAY
SILICON
UNIAXIAL STRAIN
MOSFETS
TENSILE STRESS
DEGRADATION
COMPRESSIVE STRESS
MOS DEVICES
COSTS

This publication has 2 references indexed in Scilit:

Six-band k⋅p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness
Journal of Applied Physics, 2003
Piezoresistance Effect in Germanium and Silicon
Physical Review B, 1954