A methodology for the fast and testable implementation of state diagram specifications [logic design]
- 1 April 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 20 (2) , 548-554
- https://doi.org/10.1109/jssc.1985.1052342
Abstract
A methodology is presented for the hierarchical structured design of state diagram specifications. It is based on a set of restrictions on the composition of the hierarchy that allows a design to be proven correct by construction. Furthermore, silicon primitives are introduced that permit a direct mapping of asynchronous and synchronous state diagrams. Special attention is paid to the use of scanpath testability enhancement. The design methodology and implementation technique combined facilitate a fast and area efficient integration of control structures. From the development of a DRAM controller IC, it is shown how layout design can be automated through several phases of standard cell design, permitting silicon compilation in the near future.Keywords
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