Integrated MOS four-quadrant analogue multiplier using switched-capacitor technique

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Abstract
A fully integrated four-quadrant analogue multiplier based on switched-capacitor technique for realisation of high-speed and high-density analogue LSIs was developed using a MOS VLSI process. Excellent characteristics such as low total harmonic distortion of −50 dB for two input signals of 1 Vp-p, large dynamic range of 80 dB and fast operation speed of 2 MHz clock rate were obtained. Application to convolvers and correlators is also demonstrated.