A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS
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- 1 February 2007
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01936530,p. 246-600
- https://doi.org/10.1109/isscc.2007.373386
Abstract
A fully dynamic SAR ADC is proposed that uses passive charge-sharing and an asynchronous controller to achieve low power consumption. No active circuits are needed for high-speed operation and all static power is removed, offering power consumption proportional to sampling frequency from 50MS/s down to 0. The prototype implementation in 90nm digital CMOS achieves 7.8 ENOB, 49dB SNDR at 20MS/s consuming 290 muW. This results in a FOM of 65fJ/conversion-step.Keywords
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