Application of Power Step Stress Techniques to Transistor Life Predictions

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Abstract
STEP stressing techniques have greatly aided the semiconductor device designers to achieve and verify device reliability improvements. In the application of these techniques it has been convenient to compare power step stress and constant power data with an empirically derived temperature derating curve. Several discrepancies have been observed when this comparison has been made in earlier work. This paper describes the use of an n-p-n diffused silicon mesa transistor as a vehicle in an investigatior designed to explore the validity of the power step stress technique as a means of predicting life expectancy. Two-hour power step stress was used at various combinations of current and voltage and the devices were stressed to a statistically significant failure level. Carefully determined equivalent junction temperature measurements at various bias voltages were then utilized to correlate this failure to temperature. Data is presented to show that the two major failure modes found in this transistor, namely "collector channeling" and emitter softening are dependent upon bias conditions. It is also shown that junction temperature is not uniquely determined by the absolute power level but is more dependent on the mode of operation. A unique method of plotting power aging data is introduced to demonstrate that device life is primarily determined by junction temperature. This method which employs the current-voltage coordinates of power illustrates that different current-voltage conditions promote different failure mechanisms. It further shows, however, that all of the major failure mechanisms are closely related to the junction temperature.

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